State of the art metal oxide semiconductor field effect transistors (MOSFET) are fabricated by depositing a gate region atop a semiconducting substrate, where the gate region includes a gate conductor over a gate dielectric. The gate region may be formed by first forming a gate dielectric followed by formation of a gate conductor. The gate conductor may be doped polysilicon. With polysilicon gate MOSFETS, it is important to reduce the gate carrier-depletion effect by doping the polysilicon heavily enough, particularly near the gate dielectric interface to improve MOSFET device performance. However, with the conventional manufacturing process, it is difficult to dope the polysilicon gate in such a way to minimize the gate depletion effect without compromising the optimum source and drain diffusion doping profile, because the polysilicon and source/drain diffusion are doped by the same ion implantations. It is desirable to supply additional dopant only to the polysilicon gate, but not the source/drain diffusion. One method to do this is known as selective “pre-doping” of the gate. Conventionally, selective gate doping has been accomplished by masking the layer of gate conductor using conventional photolithography followed by doping the exposed regions by ion implantation. Following doping, the gate conductor and gate dielectric are then etched to form the gate region.
A disadvantage of the above approach is that it is difficult to etch a gate polysilicon film having doped and undoped regions or regions doped by two different dopants, since the difference in dopant concentration and dopant species creates an etch bias, where the regions doped differently etch at a different rate. The etch differential, between the regions of the gate conductor results in variation of the width of the gate features. Uniformity of the width of the gate conductor is of particular importance to the manufacture of field effect transistors (FET) devices. The width of the gate is a design feature that effects maximum chip performance, so it is undesirable to introduce this source of variability. Variations in the width of the gate conductor may reduce the performance of the device to the point that an FET device fails.
Attempts to avoid the formation of an etch differential have resulted in further manufacturing difficulties. For example, in contrast to doping the gate conductor prior to etching, attempts have been made to dope the gate conductor following the etch. By doping the gate conductor region following etching, the source and drain regions of a device are exposed to the gate conductor dopant. Introducing gate dopants to the source and drain regions can adversely affect source/drain engineering.
In order to selectively implant the gate conductor and not degrade the optimized source and drain doping profile for the device performance, it is necessary to mask the areas of the source and drain in close proximity to the gate region, while leaving the tops of the gate conductor exposed to allow ion implantation of the gate dopant. Attempts to selectively implant the gate conductor while protecting the critical source/drain regions, especially when implanting multiple nested gate regions, have not accomplished the above requirements.
Conventionally, a gate dopant-masking layer 15 has been provided using a spin-on polymer that is blanket deposited atop a substrate 20 including gate regions 21, 22, as depicted in FIG. 1. The gate dopant-masking layer 15 is then etched back to expose the top surface of the gate regions 21, 22, as depicted in FIG. 2. Conventionally, etching the dopant-masking layer 15 atop gate regions 21,22 also exposes the surface of the substrate 20, which later becomes the source and drain regions of the device. The surface of the substrate is exposed because when the spin-on polymer is applied to regions of the wafer having nested gate regions 21 the thickness T1 of the dopant-masking layer 15 atop the nested gate region 21 is very close to the thickness T2 of the dopant-masking layer 15 atop the surface of the substrate 20. Therefore, since timed etch processes subject the entire masking layer 15 to the same etch rate, removing the dopant masking layer 15 atop the gate region 21 also removes the dopant masking layer 15 from regions of the substrate 20 having the same thickness as the dopant masking layer 15 atop the gate region 22.
Nested gated regions 21 are less sensitive to exposing the substrate 20 during etch back since, depending on the viscosity of the spin-on polymer, the thickness T3 of the dopant masking layer 15 positioned in the spaces between the tightly nested gates 21 is greater than the thickness of the dopant masking layer atop the substrate T2 or atop the gate regions T1. Therefore, etch back of the masking layer 15 in tightly nested gate conductor regions 21 may mask the substrate between the gate conductor structures of the tightly nested gate regions 21, as depicted in FIG. 2. Substrate masking between gate conductor structures of tightly nested gate regions is a function of the distance separating gate regions; the width of the gate conductor in the gate region; and the viscosity of the spin-on polymer solution being applied. The smaller the dimension separating adjacent gate regions, the smaller the gate conductor, and the higher the viscosity of the spin-on polymer, the higher the likelihood of substrate masking in tightly nested gate conductor regions.
In view of the above, a method of doping a gate region, which is not subjected to the disadvantages of etch bias differential encountered using conventional processing methods, and does not introduce gate conductor dopants to the source and drain regions of the device is needed. A method is also needed of providing a gate conductor dopant mask atop regions of the substrate that are in close proximity to the gate conductor of the device.